DIVIDING DEVICES WITH PRELIMINARY PREPARATION OF MULTIPLES OF THE DIVISOR

Abstract

The paper presents a division device for integers that generates a remainder and two quotient digits per clock cycle. To enable this, both forward and inverse codes of values that are multiples of the divisor (B, 2B, and 3B) are precomputed and stored in a dedicated quotient register block. During each iteration, the previous partial remainder is left-shifted by two bits (i.e., ) and compared against the stored multiples. The closest match is selected and subtracted from , yielding the next partial remainder . Based on the selected multiple, the corresponding two digits of the quotient are also determined.These operations are carried out within the Partial Remainder and Quotient Bit Generation Block (GPRaQB). The proposed architecture enables implementation of the divider using sequential, matrix-based, or pipelined circuit structures. This study focuses on dividers implemented using sequential circuits. The correctness of the proposed method is validated both through a worked example and simulation on Field-Programmable Gate Arrays (FPGAs).